Download 3D Nanoelectronic Computer Architecture and Implementation by D. Crawley, K. Nikolic, M. Forshaw PDF

By D. Crawley, K. Nikolic, M. Forshaw

It really is turning into more and more transparent that the two-dimensional structure of units on desktop chips is beginning to prevent the advance of high-performance computers. third-dimensional buildings could be had to give you the functionality required to enforce computationally extensive initiatives. three-D Nanoelectronic laptop structure and Implementation experiences the cutting-edge in nanoelectronic machine layout and fabrication and discusses the architectural features of 3D designs, together with the potential use of molecular wiring and carbon nanotube interconnections. it is a worthwhile reference for these fascinated with the layout and improvement of nanoelectronic units and know-how.

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Extra info for 3D Nanoelectronic Computer Architecture and Implementation (Series in Materials Science and Engineering)

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If the reduction in latency was such that the cache was no longer necessary, however, such area increases could be an economic proposition. A further advantage of the multibank approach could be obtained if the memory system enabled simultaneous access to more than one bank at a time. 16. The figure shows a number of memory banks connected via a crossbar switch to the machine registers. The crossbar connects memory bank data lines to machine registers. Several registers may be loaded from (or have their contents stored into) main memory in a single cycle.

2 Three-dimensional techniques Three-dimensional systems may be divided into four separate classes, each representing a distinctly different approach to their construction: (i) (ii) (iii) (iv) 3D multi-chip modules (MCM), stacked chips using connections at the edges of chips, 3D integrated circuit fabrication and stacked chips using connections across the area of chips. For completeness, a description of each class is given here but because the final two classes are likely to be of direct relevance to nanoelectronics, more attention is given to them.

As a technique for reducing power consumption, the use of activity control to switch the power to PE logic has the following advantages: (i) It has already been shown to enhance performance in SIMD arrays, so some form of activity control would be likely to be included as a matter of course. (ii) It is applicable to many technologies, including advanced CMOS, where leakage currents (as opposed to dynamic power dissipation) may form a large part of the total power consumption. However, the technique is not without some possible disadvantages.

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