By Daniel J. Sorin, Mark D. Hill, David A. Wood
Many smooth desktops and so much multicore chips (chip multiprocessors) help shared reminiscence in undefined. In a shared reminiscence approach, all of the processor cores may perhaps learn and write to a unmarried shared deal with area. For a shared reminiscence computer, the reminiscence consistency version defines the architecturally seen habit of its reminiscence approach. Consistency definitions supply ideas approximately quite a bit and shops (or reminiscence reads and writes) and the way they act upon reminiscence. As a part of helping a reminiscence consistency version, many machines additionally offer cache coherence protocols that make sure that a number of cached copies of information are saved updated. The objective of this primer is to supply readers with a easy realizing of consistency and coherence. This realizing comprises either the problems that needs to be solved in addition to various recommendations. We current either highlevel suggestions in addition to particular, concrete examples from real-world platforms. desk of Contents: Preface / advent to Consistency and Coherence / Coherence fundamentals / reminiscence Consistency Motivation and Sequential Consistency / overall shop Order and the x86 reminiscence version / comfy reminiscence Consistency / Coherence Protocols / Snooping Coherence Protocols / listing Coherence Protocols / complex issues in Coherence / writer Biographies
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Additional info for A Primer on Memory Consistency and Cache Coherence
For example, a simple 5-stage in-order pipeline with branch prediction can be used. C1 C2 SWITCH MEMORY Cn Each core Ci seeks to do its next memory access in its program order
4      Coherence pertains to all storage structures that hold blocks from the shared address space. These structures include the L1 data cache, L2 cache, shared last-level cache (LLC), and main memory. , coherence is not architecturally visible). Strictly speaking, a system could be incoherent and still be correct if it adhered to the specified memory consistency model. , it is difficult to imagine a practical system that is consistent but not coherent), it has a highly important corollary: the memory consistency model places no explicit constraints on coherence or the protocol used to enforce it.
5 A LITTLE SC FORMALISM In this section, we define SC more precisely, especially to allow us to compare SC with the weaker consistency models in the next two chapters. We adopt the formalism of Weaver and Germond [17 (Appendix D)] with the following notation: L(a) and S(a) represent a load and a store, respectively, to address a. Orders