By Kunle Olukotun
Chip multiprocessors - often known as multi-core microprocessors or CMPs for brief - are actually the single solution to construct high-performance microprocessors, for numerous purposes. huge uniprocessors are not any longer scaling in functionality, since it is barely attainable to extract a restricted volume of parallelism from a regular guide circulation utilizing traditional superscalar guideline factor strategies. additionally, one can't easily ratchet up the clock pace on modern-day processors, or the ability dissipation turns into prohibitive in all yet water-cooled structures. Compounding those difficulties is the straightforward proven fact that with the sizeable numbers of transistors to be had on modern day microprocessor chips, it really is too high priced to layout and debug ever-larger processors each year or . CMPs keep away from those difficulties via filling up a processor die with a number of, really less complicated processor cores rather than only one large middle. the precise measurement of a CMPs cores can fluctuate from extremely simple pipelines to reasonably advanced superscalar processors, yet as soon as a middle has been chosen the CMPs functionality can simply scale throughout silicon method generations just by stamping down extra copies of the hard-to-design, high-speed processor middle in each one successive chip iteration. additionally, parallel code execution, bought via spreading a number of threads of execution around the quite a few cores, can in achieving considerably better functionality than will be attainable utilizing just a unmarried middle. whereas parallel threads are already universal in lots of precious workloads, there are nonetheless vital workloads which are challenging to divide into parallel threads. The low inter-processor communique latency among the cores in a CMP is helping make a much broader diversity of functions doable applicants for parallel execution than was once attainable with traditional, multi-chip multiprocessors; however, constrained parallelism in key purposes is the most issue restricting attractiveness of CMPs in a few sorts of structures.
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Extra info for Chip Multiprocessor Architecture: Techniques to Improve Throughput and Latency
2 Example 2: The Niagara Server CMP The Niagara processor from Sun Microsystems , illustrated in Fig. 6: Niagara-1 block diagram. 7: Niagara core pipeline. performance/Watt on server workloads. Unlike the Piranha, the Niagara CMP became an actual product (the Sun UltraSPARC T1); it has therefore been investigated in much more detail using real silicon. Like Piranha, Niagara employs eight scalar, shallow pipeline processors on a single die. The pipeline on Niagara is quite shallow, only six stages deep, and employs very little speculation, eschewing even the branch prediction that was present in Piranha.
4: Piranha’s (a) speedup and (b) L1 miss breakdown for OLTP. vs. 6. 45. Validating the earlier discussion on the merits of designing a CMP from larger numbers of simple cores, the integration of eight of the Piranha CPUs into the single chip Piranha (P8) leads to Piranha outperforming OOO by almost a factor of 3. As shown in Fig. 4(a), the reason for Piranha’s exceptional performance on OLTP is that it achieves a speedup of nearly seven with eight on-chip CPUs relative to a single CPU (P1). This speedup arises from the abundance of thread-level parallelism in OLTP, along with the extremely tight-coupling of the on-chip CPUs through the shared second-level cache (leading to small communication latencies), and the effectiveness of the on-chip caches in Piranha.
The instruction and data caches have sufficient bandwidth left for more threads. The L2 cache utilization can support a modestly higher load as well. While it is possible to use multiple-issue cores to generate more memory references per cycle to the primary caches, a technique measured in , a more effective method to balance the pipeline and cache utilization may be to have multiple single-issue pipelines share primary caches. Addressing the memory bottleneck is more difficult. Niagara devotes a very large number of pins to the four DDR2 SDRAM memory channels, so without a change in memory technology, attacking the memory bottleneck would be difficult.